FPGA Bridging Fault Detection and Location via Differential I{DDQ}

Standard IDDQ testing is limited by the ability to distinguish a small fault current from a large background leakage current: this limitation is overcome in FPGAs by differential IDDQ testing. Partitioning of interconnects—dividing the interconnect resources of an FPGA into groups—further increases the detectability of a fault current. Fault location can be achieved by iteratively applying partitioned differential IDDQ testing to eliminate fault-free nets. The location algorithm, easily automated, requires very few configurations and IDDQ measurements, logarithmic to the number of initially-suspected faulty nets.